1. Field of the Invention
The present invention relates to a semiconductor memory device having plural memory arrays on a semiconductor chip.
2. Description of the Related Art
A semiconductor memory device having a memory array on a semiconductor chip is known. With an increase of a level of integration of the semiconductor memory on the chip, there is a demand to reduce a current consumption of memory cells constituting the memory array and to lower an operating voltage of the memory array. The semiconductor memory device is provided with a bias-voltage supply circuit which is adapted to suit the demand. The bias-voltage supply circuit produces a lowered operating voltage from a source voltage of an external battery and supplies the lowered operating voltage to the memory array of the chip.
It is necessary to pass a comparatively large amount of current through the bias-voltage supply circuit in order to avoid a malfunction of the bias-voltage supply circuit caused by noise. However, a current consumption of the bias-voltage supply circuit when the semiconductor memory device is placed in a waiting condition (which will be called a waiting-condition current consumption) is a problem in reducing the current consumption of the semiconductor memory device.
For example, Japanese Laid-Open Patent Applications No. 9-17181, No. 6-242847 and No. 5-206752 disclose bias-voltage supply circuits of semiconductor devices adapted to lower the waiting-condition current consumption.
However, the bias-voltage supply circuits of the above publications are not effective in reducing the waiting-condition current consumption of the semiconductor device when the semiconductor device continues to operate in a standby mode for a long time.
A semiconductor memory device of a certain type is able to operate in a sleep mode, instead of the standby mode, when it is needed to stay in a waiting condition for a long time. The sleep mode is intended to eliminate the problem of the bias-voltage supply circuits of the above publications.
In the above-mentioned semiconductor memory device, when the semiconductor memory device is instructed by a CPU (central processing unit), the semiconductor memory device is set in the sleep mode. During the sleep mode, the operation of the bias-voltage supply circuit is stopped, and the waiting-condition current consumption as in the bias-voltage supply circuits of the above publications can be reduced.
In recent years, a semiconductor memory device having plural memory arrays on a semiconductor chip has been developed. The memory arrays of the semiconductor memory device of this type include, for example, a program memory array storing a program and a data memory array storing data.
However, in the semiconductor memory device of the above-mentioned type, it is necessary that a certain period is passed after a receipt of a cancel command to cancel the sleep mode, in order for the bias-voltage supply circuits to start supplying the operating voltage to the memory arrays in a stable condition. After such a delay of a certain period, the supply of the operating voltage to the memory arrays by the bias-voltage supply circuits is started. After the delay of the period, the semiconductor memory device of this type is placed in the active condition, and then the memory arrays are accessible to the CPU.
Therefore, during the period, the CPU is unable to access the memory arrays although the cancel command to cancel the sleep mode is already transmitted to the control circuit. Hence, the semiconductor memory device of this type during the sleep mode causes a difficulty in speedily accessing the memory arrays after the receiving of the cancel command from the CPU.